A cache memory may be a set-associative cache memory. The set-associative cache memory is divided into a predetermined amount of cache sets. Each cache set comprises a predetermined number of cache lines, the predetermined number of cache lines referred to as the associativity of the cache memory. The particular cache set, where data is written to, is determined by an address of the data, whereas the associativity of the cache represents the number of cache lines within the determined cache set available for the particular data address.
Input-Output data transfers, also referred to as IO-data transfers, are commonly processed by direct memory access transfers, also referred to as DMA transfers, going from the IO-device to, for example, the main memory.
With cache injection bus-actors like IO-devices and potentially also processing units or data copy engines can explicitly specify a cache location to which they want to push data. Cache injection is a data source driven technique that reduces memory latency and data transfer delays by pushing cache injection data directly into cache memory, ideally into cache memory tightly coupled to a processor unit processing the data.
U.S. Pat. No. 6,711,650 B1 discloses a mechanism in a cache memory determining if a bus operation is a data transfer from a first memory to a second memory. If the bus operation is such a data transfer, a determination is made in the cache memory as to whether or not the cache memory includes a copy of data from the data transfer. If a copy of data from the data transfer is not included in the cache memory, a cache line is allocated in the cache memory to store a copy of data from the data transfer. If the cache memory does include a copy of data from the data transfer, the cache memory updates the copy of data within the cache memory with the new data during the data transfer.
US2006/0064518 A1 discloses a method and apparatus for managing cache injection in a multi-processor system. The method and apparatus either detect the target processor of a DMA completion routine that typically processes the DMA data or direct processing of the DMA completion routine to a particular processor, thereby enabling cache injection to a cache that is coupled with the particular processor that processes the DMA data. The target processor may be identified by determining the processor handling the interrupt that occurs on completion of the DMA transfer.
U.S. Pat. No. 5,293,608 discloses a system and method for optimizing the utilization of a cache memory in an input/output controller in a computer system. The optimization system calculates a demotion time where the demotion time is an approximation of the length of the time that a track of data will reside in cache memory after its last input/output request from a central processing unit. An elapsed time between successive input/output requests from the central processing unit for the requested track of data is determined and compared to the demotion time. If the elapsed time is greater than the demotion time, the corresponding track of data associated to the elapsed time is referred to as not efficient cache user and is inhibited from being loaded into the cache memory, thereby displacing potentially more efficient uses of cache memory.
U.S. Pat. No. 7,246,205 B2 discloses monitoring of performance parameters to enable or disable push cache operations depending on whether the performance parameters are within a predetermined range. The patent discloses another method which monitors an amount of credits associated with a device and enables or disables push cache operations dependent upon whether the device has sufficient remaining credits.
Consequently, it is a challenge to provide a memory device comprising a mechanism which enables efficient cache use.